1 MENU BIOS DAN POST

---

Jangan Lupa Tinggalkan Komentar Kalian Ya...!!!

---

FIGURE B-2 BIOS Utility Menu Tree

[ D ]

BIOS Main Menu Screens

FIGURE B-4 BIOS Setup Utility: Main - Product Information

BIOS Advanced Menu Screens

FIGURE B-6 BIOS Setup Utility: Advanced - CPU Settings

FIGURE B-7 BIOS Setup Utility: Advanced - System Memory Settings

FIGURE B-8 BIOS Setup Utility: Advanced - IDE Configuration

FIGURE B-9 BIOS Setup Utility: Advanced - Super IO Configuration

FIGURE B-10 BIOS Setup Utility: Advanced - Trusted Computing

FIGURE B-11 Bios Setup Utility: Advanced - USB Configuration

FIGURE B-12 BIOS Setup Utility: Advanced - USB Configuration 2

FIGURE B-13 BIOS Setup Utility: Advanced- PCI Configuration

FIGURE B-14 BIOS Setup Utility: Advanced- MPS Configuration

FIGURE B-15 BIOS Setup Utility: Advanced- Event Log Configuration

B.3.1.3 BIOS Boot Menu Screens

The BIOS Boot screens enable you to configure the boot device priority (hard drives and the optical media drives).

The Sun Netra X4250 server has the following BIOS Boot screens.

FIGURE B-16 BIOS Setup Utility: Boot

FIGURE B-17 BIOS Setup Utility: Boot Settings Configuration

FIGURE B-18 BIOS Setup Utility: Boot Device Priority

FIGURE B-19 BIOS Setup Utility: Boot Hard Drives

FIGURE B-20 BIOS Setup Utility: Boot CD/DVD Drives

BIOS Server Menu Screens

FIGURE B-22 BIOS Setup Utility: Server - Bottom of Scroll

FIGURE B-23 BIOS Setup Utility: Server - LAN Configuration

FIGURE B-24 BIOS Setup Utility: Server - LAN Configuration - Reset SP (BMC) Password

FIGURE B-25 BIOS Setup Utility: Server - Enable Remote Access

FIGURE B-26 Bios Setup Utility: Server - View SP Event Log

FIGURE B-27 BIOS Setup Utility: Server - Clear SP Event Log

B.3.1.5 BIOS Security Menu Screens

The BIOS Security screens enable you to set or change the user and supervisor passwords.

The Sun Netra X4250 server has the following BIOS Security screens:

FIGURE B-28 BIOS Setup Utility: Security -Menu

B.3.1.6 BIOS Exit Menu Screens

The BIOS Exit screens enable you to save changes and exit, discard changes and exit, discard changes, or load optimal or fail-safe defaults.

The Sun Netra X4250 server has the following BIOS Exit screens:

FIGURE B-29 BIOS Setup Utility: Exit

FIGURE B-30 BIOS Setup Utility: Exit - Save Configuration Changes

FIGURE B-31 BIOS Setup Utility: Exit - Discard Changes

FIGURE B-32 BIOS Setup Utility: Exit - Discard Changes, Do Not Exit

FIGURE B-33 BIOS Setup Utility: Exit - Load Optimal Defaults

FIGURE B-34 BIOS Setup Utility: Exit - Load Fail-Safe Defaults

---

B.4 Viewing Event Logs

Use this procedure to view the BIOS event log and the SP system event log.

1. To turn on main power mode (all components powered on) if necessary, use a ball point pen or other stylus to press and release the Power button on the server front panel (FIGURE 1-6).

When main power is applied to the full server, the Power OK LED next to the Power button lights and remains lit.

2. Enter the BIOS Setup utility by pressing the F2 key while the system is performing the power-on self-test (POST).

The BIOS Main menu screen is displayed (FIGURE B-4).

3. View the BIOS event log.

a. From the BIOS Main menu screen, select Advanced.

The Advanced Settings screen is displayed (FIGURE B-5).

b. From the Advanced Settings screen, select Event Log Configuration.

The Event Logging Details screen is displayed (FIGURE B-15).

c. From the Event Logging Details screen, select View Event Log.

All unread events are displayed (FIGURE B-35).

4. View the SP system event log.

a. From the BIOS Main menu screen, select Server.

The Server screen is displayed (FIGURE B-21).

b. From the Server screen, select View SP System Event Log.

All events are displayed (FIGURE B-35).

FIGURE B-35 Event Log Screen

---

B.5 Setting Watchdog Timers

Gunakan prosedur ini untuk mengatur baik SP BIOS timer pengawas atau SP Timer OS Watchdog.

1. Masukkan utilitas Pengaturan BIOS dengan menekan tombol F2 ketika sistem melakukan power-on self-test (POST).

Layar menu BIOS utama ditampilkan (GAMBAR B-4).

2. Dari layar menu BIOS Main, pilih Server.

3. Layar Server ditampilkan (GAMBAR B-21).

4. Dari layar Server, pilih salah SP BIOS pengawas Aksi Timer atau SP OS Aksi Watchdog Timer.

5. Layar Options akan ditampilkan (GAMBAR B-36).

6. Dari layar Options, pilih tindakan yang diinginkan.

7. Dari layar Server, mengatur baik SP BIOS Waktu Watchdog Out ​​atau SP Waktu OS pengawas Out nilai, jika ada.

8. Simpan perubahan dan keluar Utilitas BIOS dengan menekan F10.

Sebagai alternatif, Anda dapat memilih layar Exit, kemudian pilih Save Changes and Exit.

 

---

B.6 Power-On Self-Test (POST)

Sistem BIOS menyediakan power-on self-test dasar. Perangkat dasar yang diperlukan untuk server untuk beroperasi diperiksa, memori diuji, disk controller dan disk terlampir diperiksa dan disebutkan, dan dua Intel dual Gigabit Ethernet controller diinisialisasi.
Kemajuan self-test ditunjukkan dengan serangkaian kode POST. Kode-kode ini ditampilkan di sudut kanan bawah layar VGA sistem (setelah self-test telah berkembang cukup jauh untuk menginisialisasi sistem video). Namun, kode ini ditampilkan sebagai self-test berjalan dan gulir off dari layar terlalu cepat untuk dibaca. Sebuah metode alternatif menampilkan kode POST adalah untuk mengarahkan output dari konsol ke port serial (lihat Keluaran Mengarahkan Console).

Bagaimana BIOS POST Pengujian Memori Bekerja

POST BIOS pengujian memori dilakukan sebagai berikut:

1. The megabyte pertama DRAM diuji oleh BIOS sebelum kode BIOS dibayangi (yaitu, disalin dari ROM ke DRAM).

2. Setelah melaksanakan keluar dari DRAM, BIOS melakukan tes memori sederhana (write-dibaca dari setiap lokasi dengan pola 55aa55aa).
Catatan - Mengaktifkan Boot Cepat menyebabkan BIOS untuk melewati tes memori. Lihat Mengubah Pilihan POST untuk informasi lebih lanjut.


Catatan - Karena server dapat berisi hingga 64 MByte memori, tes memori dapat berlangsung beberapa menit. Anda dapat membatalkan pengujian POST dengan menekan tombol apa saja saat POST.

3. BIOS jajak pendapat pengendali memori untuk memori kesalahan diperbaiki dan uncorrectable dan log kesalahan-kesalahan ke dalam prosesor layanan.
B.6.2 Mengarahkan Console output

Gunakan petunjuk berikut untuk mengakses prosesor layanan dan redirect output konsol sehingga kode POST BIOS dapat dibaca.

1. Menginisialisasi utilitas Pengaturan BIOS dengan menekan tombol F2 ketika sistem melakukan power-on self-test (POST).

Layar menu BIOS utama ditampilkan.

2. Pilih tab menu Advanced.

Layar Pengaturan Lanjutan ditampilkan.

3. Pilih IPMI Konfigurasi 2.0.

The IPMI 2.0 Layar Configuration akan ditampilkan.

4. Pilih item menu Konfigurasi LAN.

Layar Konfigurasi LAN menampilkan alamat IP prosesor layanan.

5. Untuk mengkonfigurasi alamat IP prosesor selular (opsional):

a. Pilih opsi Tugas IP yang ingin Anda gunakan (DHCP atau Static).

    Jika Anda memilih DHCP, alamat IP server yang diambil dari jaringan Anda DHCP server dan         ditampilkan dengan menggunakan format berikut:
    Saat ini IP address di BMC: xxx.xxx.xxx.xxx

    Jika Anda memilih Static untuk menetapkan alamat IP secara manual, lakukan langkah-langkah berikut:

i.  Ketik alamat IP di bidang Alamat IP.

    Anda juga dapat memasukkan pengaturan subnet mask dan default gateway di bidangnya masing-masing.

ii. Pilih Komit dan tekan Kembali untuk melakukan perubahan.

iii. Pilih Refresh dan tekan Enter untuk melihat pengaturan baru Anda ditampilkan dalam alamat IP saat ini di lapangan BMC.

6. Mulai browser web dan ketik alamat IP prosesor jasa dalam bidang URL browser.

7. Ketika Anda diminta untuk nama pengguna dan password, ketik berikut:

    Nama Pengguna: root

    Sandi: sandi

The Lights Out Terpadu Sun Manager layar GUI utama ditampilkan.

8. Klik tab Remote Control.

9. Klik tab Redirection.

10. Mengatur kedalaman warna untuk konsol redirection pada 6 atau 8 bit.

Klik tombol Mulai Redirection.

11. Ketika Anda diminta untuk nama pengguna dan password, ketik berikut:

     Nama Pengguna: root

     Sandi: sandi

Layar POST saat ini akan ditampilkan.
Pilihan POST Mengubah

Instruksi-instruksi ini opsional, tetapi Anda dapat menggunakannya untuk mengubah operasi yang server melakukan pengujian selama POST. Untuk mengubah opsi POST:

1. Menginisialisasi utilitas Pengaturan BIOS dengan menekan tombol F2 ketika sistem melakukan power-on self-test (POST).

Layar menu BIOS utama ditampilkan (GAMBAR B-3).

2. Pilih Boot.

The Boot Pengaturan layar ditampilkan (GAMBAR B-16).

3. Pilih Boot Konfigurasi Pengaturan.

The Boot Pengaturan layar Configuration akan ditampilkan (GAMBAR B-17).

4. Pada layar Boot Pengaturan Konfigurasi, ada beberapa pilihan yang Anda dapat mengaktifkan atau menonaktifkan:

    Boot Cepat - Opsi ini dinonaktifkan secara default. Jika Anda mengaktifkan opsi ini, BIOS melompat tes tertentu saat boot, seperti uji memori yang luas. Tindakan ini mengurangi waktu yang diperlukan untuk sistem untuk boot.

    Boot tenang - Opsi ini dinonaktifkan secara default. Jika Anda mengaktifkan pilihan ini, Sun Microsystems logo ditampilkan bukan kode POST.

    Add On Modus ROM Tampilan - Opsi ini diatur ke Force BIOS secara default. Opsi ini hanya berlaku jika Anda telah mengaktifkan opsi Boot tenang, tetapi opsi ini mengontrol apakah output dari ROM Opsi ditampilkan. Kedua pengaturan untuk opsi ini adalah sebagai berikut:

Angkatan BIOS - Lepaskan logo Sun dan output display Option ROM.

Jauhkan Lancar - Jangan menghapus logo Sun. Output Option ROM tidak ditampilkan.

    Boot Num-Lock - Pilihan ini secara default (keyboard Num-Lock diaktifkan selama boot). Jika Anda mengatur ini ke off, keyboard Num-Lock tidak diaktifkan saat boot.

    Tunggu F1 jika Kesalahan - Opsi ini dinonaktifkan secara default. Jika Anda mengaktifkan opsi ini, sistem akan berhenti jika kesalahan ditemukan selama POST dan hanya akan dilanjutkan bila Anda menekan tombol F1.

    Interrupt 19 Capture - Pilihan ini disediakan untuk penggunaan masa depan. Jangan berubah.

    Standar Boot Order - Surat-surat dalam kurung merupakan perangkat boot. Untuk melihat surat-surat yang ditetapkan, posisi kursor di atas lapangan dan membaca definisi di sisi kanan layar.

POST Kode

TABEL B-3 berisi deskripsi dari masing-masing kode POST, tercantum dalam urutan yang sama di mana mereka dihasilkan. Kode-kode POST muncul sebagai string empat digit yang merupakan kombinasi dari dua digit output dari SD I / O port 80 dan dua-digit output dari sekunder I / O port 81. Dalam kode POST tercantum dalam TABEL B-3, dua digit pertama adalah dari port 81 dan dua digit terakhir adalah dari port

Post Code	Description
00d0	Coming out of POR, PCI configuration space initialization, enabling 8111’s SMBus.
00d1	Keyboard controller BAT, waking up from PM, saving power-on CPUID in scratch CMOS.
00d2	Disabling cache, full memory sizing, and verifying that flat mode is enabled.
00d3	Memory detections and sizing in boot block, cache disabled, I/O APIC enabled.
01d4	Testing base 512KB memory. Adjusting policies and cache first 8MB.
01d5	Boot block code is copied from ROM to lower RAM. BIOS is now executing out of RAM.
01d6	Key sequence and OEM specific method is checked to determine if BIOS recovery is forced. If next code is E0, BIOS recovery is being executed. Main BIOS checksum is tested.
01d7	Restoring CPUID: Moving boot block-runtime interface module to RAM: determining whether to execute serial flash.
01d8	Decompressing runtime module into RAM. Storing CPUID information in memory.
01d9	Copying main BIOS into memory.
01da	Giving control to BIOS POST.
0004	Checking CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. If the CMOS checksum is bad, update CMOS with power-on default values.
00c2	Setting up boot strap processor for POST. This action includes frequency calculation, loading BSP microcode, and applying user requested value for GART Error Reporting setup question.
00c3	Errata workarounds applied to the BSP (No. 78 and No. 110).
00c6	Re-enable cache for boot strap processor, and apply workarounds in the BSP for errata No. 106, No. 107, No. 69, and No. 63 if appropriate.
00c7	HT sets link frequencies and widths to their final values.
000a	Initializing the 8042 compatible keyboard controller.
000c	Detecting the presence of keyboard in KBC port.
000e	Testing and initialization of different input devices. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1.
8600	Preparing CPU for booting to OS by copying all of the context of the BSP to all application processors present. Note: APs are left in the CLI HLT state.
de00	Preparing CPU for booting to OS by copying all of the context of the BSP to all application processors present. Note: APs are left in the CLI HLT state.
8613	Initializing PM regs and PM PCI regs at early-POST. Initialize multihost bridge, if system supports it. Setup ECC options before memory clearing. Enable PCI-X clock lines in the 8131.
0024	Decompressing and initializing any platform specific BIOS modules.
862a	BBS ROM initialization.
002a	Generic Device Initialization Manager (DIM) - Disable all devices.
042a	ISA PnP devices - Disable all devices.
052a	PCI devices - Disable all devices.
122a	ISA devices - Static device initialization.
152a	PCI devices - Static device initialization.
252a	PCI devices - Output device initialization.
202c	Initializing different devices. Detecting and initializing the video adapter installed in the system that have optional ROMs.
002e	Initializing all the output devices.
0033	Initializing the silent boot module. Set the window for displaying text information.
0037	Displaying sign-on message, CPU information, setup key message, and any OEM specific information.
4538	PCI devices - IPL device initialization.
5538	PCI devices - General device initialization.
8600	Preparing CPU for booting to OS by copying all of the context of the BSP to all application processors present. Note: APs are left in the CLI HLT state.

B.6.5 POST Code Checkpoints

The POST code checkpoints are the largest set of checkpoints during the BIOS pre-boot process. TABLE B-4 describes the type of checkpoints that might occur during the POST portion of the BIOS. These two-digit checkpoints are the output from primary I/O port 80.

TABLE B-4 POST Code Checkpoints

Post Code	Description
03	Global initialization before the execution of actual BIOS POST. Initialize BIOS Data Area (BDA) variables to their default values. Initialize POST data variables. NMI, parity, video for EGA, and DMA controllers are disabled at this point.
04	Checks CMOS diagnostic byte to verify that battery power and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS with power-on default values and clear passwords. Initialize status register A. Initializes data variables that are based on CMOS setup questions. Initializes both the 8259 compatible PICs in the system.
05	Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table.
06	Does read-write test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch vector to POSTINT1ChHandlerBlock.
C0	Early CPU Init Start-Disable Cache-Init Local APIC.
C1	Sets up boot strap processor information.
C2	Sets up boot strap processor for POST. This action includes frequency calculation, loading BSP microcode, and applying user requested value for GART Error Reporting setup question.
C3	Errata workarounds applied to the BSP (No. 78 & No. 110).
C5	Enumerates and sets up application processors. This action includes microcode loading, and workarounds for errata (No. 78, No. 110, No. 106, No. 107, No. 69, No. 63).
C6	Re-enable cache for boot strap processor, and apply workarounds in the BSP for errata No. 106, No. 107, No. 69, and No. 63 if appropriate. In case of mixed CPU steppings, errors are sought and logged, and an appropriate frequency for all CPUs is found and applied. Note: APs are left in the CLI HLT state.
C7	The HT sets link frequencies and widths to their final values. This routine gets called after CPU frequency has been calculated to prevent bad programming.
0A	Initializes the 8042 compatible keyboard controller.
0B	Detects the presence of PS/2 mouse.
0C	Detects the presence of keyboard in KBC port.
0E	Testing and initialization of different input Devices. Also, update the kernel variables. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1. Decompress all available language, BIOS logo, and silent logo modules.
13	Initializes PM regs and PM PCI regs at Early-POST. Initialize multihost bridge, if system supports it. Set up ECC options before memory clearing. REDIRECTION causes corrected data to written to RAM immediately. CHIPKILL provides 4 bit error det/corr of x4 type memory. Enable PCI-X clock lines in the 8131.
20	Relocates all the CPUs to a unique SMBASE address. The BSP will be set to have its entry point at A000:0. If fewer than 5 CPU sockets are present on a board, subsequent CPUs entry points will be separated by 8000h bytes. If more than 4 CPU sockets are present, entry points are separated by 200h bytes. CPU module will be responsible for the relocation of the CPU to correct address. Note: APs are left in the INIT state.
24	Decompresses and initializes any platform specific BIOS modules.
30	Initializes System Management Interrupt.
2A	Initializes different devices through DIM.
2C	Initializes different devices. Detects and initializes the video adapter installed in the system that have optional ROMs.
2E	Initializes all the output devices.
31	Allocates memory for ADM module and decompress it. Gives control to ADM module for initialization. Initializes language and font modules for ADM. Activate ADM module.
33	Initializes the silent boot module. Set the window for displaying text information.
37	Displaying sign-on message, CPU information, setup key message, and any OEM specific information.
38	Initializes different devices through DIM.
39	Initializes DMAC-1 and DMAC-2.
3A	Initializes RTC date and time.
3B	Tests for total memory installed in the system. Also, Check for DEL or ESC keys to limit memory test. Displays total memory in the system.
3C	By this point, RAM read-write test is completed, program memory holes or handle any adjustments needed in RAM size with respect to NB. Tests if HT module found an error in boot block and CPU compatibility for MP environment.
40	Detects different devices (Parallel ports, serial ports, and coprocessor in CPU, etc.) successfully installed in the system and update the BDA, EBDA, etc.
50	Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if needed.
52	Updates CMOS memory size from memory found in memory test. Allocates memory for Extended BIOS Data Area from base memory.
60	Initializes NUM-LOCK status and programs the KBD typematic rate.
75	Initializes Int-13 and prepares for IPL detection.
78	Initializes IPL devices controlled by BIOS and option ROMs.
7A	Initializes remaining option ROMs.
7C	Generates and writes contents of ESCD in NVRAM.
84	Logs errors encountered during POST.
85	Displays errors to the user and gets the user response for error.
87	Executes BIOS setup if needed or requested.
8C	After all device initialization is done, programmed any user selectable parameters relating to NB/SB, such as timing parameters, noncacheable regions, and the shadow RAM cacheability, and do any other NB/SB/PCIX/OEM specific programming needed during Late-POST. Background scrubbing for DRAM, and L1 and L2 caches are set up based on setup questions. Get the DRAM scrub limits from each node. Workaround for erratum No. 101 applied here.
8D	Builds ACPI tables (if ACPI is supported).
8E	Programs the peripheral parameters. Enable/Disable NMI as selected.
90	Late POST initialization of system management interrupt.
A0	Checks boot password if installed.
A1	Clean-up work needed before booting to OS.
A2	Takes care of runtime image preparation for different BIOS modules. Fills the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ routing table. Prepares the runtime language module. Disables the system configuration display if needed.
A4	Initializes runtime language module.
A7	Displays the system configuration screen if enabled. Initializes the CPUs before boot, which includes the programming of the MTRRs.
A8	Prepares CPU for OS boot including final MTRR values.
A9	Waits for user input at config display if needed.
AA	Uninstalls POST INT1Ch vector and INT09h vector. Deinitializes the ADM module.
AB	Prepares BBS for Int 19 boot.
AC	Any kind of chipsets (NB/SB) specific programming needed during End- POST, just before giving control to runtime code booting to OS. Programmed the system BIOS (0F0000h shadow RAM) cacheability. Ported to handle any OEM specific programming needed during End-POST. Copies OEM specific data from POST_DSEG to RUN_CSEG.
B1	Saves system context for ACPI.
00	Prepares CPU for booting to OS by copying all of the context of the BSP to all application processors present. Note: APs are left in the CLIHLT state.
61-70	OEM POST error. This range is reserved for chipset vendors and system manufacturers. The error associated with this value might be different from one platform to the next.